1. Field of the Invention
The present invention relates to a clock synchronizing circuit and, more particularly, to a clock synchronizing circuit capable of reducing power consumption.
2. Background of the Related Art
FIG. 1 is a schematic block of a related clock synchronizing circuit. As illustrated in FIG. 1, the related clock synchronizing circuit includes a phase comparator 5, a charge pump 6, a phase compensator 2, and a controller 4.
The phase comparator 5 compares an external clock input signal with an internal clock signal which is obtained by phase-compensating the external clock signal, and a phase error detecting signal (fast or slow). The charge pump 6 is selectively charged or discharged depending on the phase error detecting signal of the phase comparator 5, and outputs a charge signal for phase error compensation. The phase compensator 2 compensates the phase error of the external clock signal input through an input buffer 1 using the charge signal from the charge pump 6. The phase-compensated external clock signal is received by output buffer 3, which converts the phase-compensated external clock signal to an internal clock signal. The controller 4 controls the phase comparators, the charge pump 6 and the phase comparator.
The phase comparator 5 compares the phase of the external clock signal with the phase of a feedback clock signal derived from the internal clock signal. The phase comparator 5 outputs a high signal if the phase of the external clock signal is faster than the phase of the feedback clock signal. The phase comparator 5 outputs a low signal if the phase of the external clock signal is slower than the phase of the feedback clock signal.
FIG. 2 shows operational waveforms of a related clock phase comparator 5. Referring to FIG. 2, when the external clock signal is low at a time corresponding to a rising edge(RE) of the feedback clock signal, the output of the clock phase comparator 5 becomes low, so that the phase error detecting signal for the input external clock signal becomes slow. When the input external clock input is high at a time corresponding to a RE of the feedback clock signal, the output of the clock phase comparator 5 becomes high, so that the phase error detecting signal for the input external clock signal becomes fast.
As stated above, the related clock synchronizing circuit has several problems. Since the phase comparator 5 of the related clock synchronizing circuit only determines whether the phase of the external clock signal is faster than the phase of the reference clock signal, the phase control system continually compensates the phase of the external clock signal, even when their respective phases are substantially synchronized. This increases unnecessary power consumption. In particular, such unnecessary power consumption is caused during a standby state.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.